The present invention relates to a method for controlling a data transmission.
In contemporary data transmission means, particularly in personal computers, what is known as a PCI bus (Peripheral Component Interconnect) is set up for a connection of peripheral means such as an LAN (Local Area Network). The peripheral means are connected to the PCI bus via defined interfaces which are controlled via what are known as I/O controllers. For a data transfer between the peripheral means and other units such as a processor unit or a main memory connected to the processor unit via a processor bus, for example, the PCI bus is connected to the processor bus via a coupling means frequently referred to as a bridge.
The data sheet "82439HX System Controller (TXC)" of the firm Intel (July 1996, order number 290551-001, p. 5 and 6 in particular) teaches such a bridge which connects a PCI bus to a processor bus (processor host bus) and a central memory (main memory). The bridge comprises two temporary storage units for a data transfer between the PCI bus and a processor unit, or respectively, the main memory. Those data which are transmitted from the processor unit to a peripheral means connected to the PCI bus, or vice versa, on the basis of an initiative of the processor unit are temporarily stored in a first temporary storage unit. Those data which are transmitted to the main memory from a peripheral means connected to the PCI bus, or vice versa, on the basis of an initiative of said means are temporarily stored in a second temporary storage unit.
The first and the second temporary storage units are respectively fashioned as FIFO (First In First Out) memories in which the data to be transmitted are stored together with an address identifying the respective peripheral means.